Novel Approach for implementation BISR (Built In Self Repair) With Redundancies in a System On-Chip For SRAMS

B. NAGAMANI; D. MUTHILINGAM

Novel Approach for implementation BISR (Built In Self Repair) With Redundancies in a System On-Chip For SRAMS

Authors: B. NAGAMANI, D. MUTHILINGAM

Unique Paper ID: 144657
Volume: 4
Issue: 1
PageNo: 304-307

Keywords: Redundancy Analysis SoC SRAM MBISR.

Abstract:
Therefore, we implemented an MBISR generator called BRAINS+, which automatically generates register transfer level MBISR circuits for SoC designers. The MBISR circuit is based on a redundancy analysis (RA) algorithm that enhances the essential spare pivoting algorithm, with a more flexible spare architecture, which can configure the same spare to a row, a column, or a rectangle to fit failure patterns more efficiently. The proposed MBISR circuit is small, and it supports at-speed test without timing-penalty during normal operation, e.g., with a typical 0.13Î¼m complementary metal- oxide-semiconductor technology, it can run at 333 MHz for a 512 Kb memory with four spare elements (rows and/or columns), and the MBISR area overhead is only 0.36%. With its low area overhead and zero test-time penalty, the MBISR can easily be applied to multiple memories with a distributed RA scheme. Compared with recent studies, the proposed scheme is better in not only test-time but also area overhead.

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Cite This Article

ISSN: 2349-6002
Volume: 4
Issue: 1
PageNo: 304-307

Novel Approach for implementation BISR (Built In Self Repair) With Redundancies in a System On-Chip For SRAMS

Available:https://ijirt.org/Article?manuscript=144657

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UGC Approved
Journal no 47859

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