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@article{145199,
        author = {Shaik Sameera Bannu and S.Priyanka},
        title = {ADDER ENCHANCEMENT TECHINQUES},
        journal = {International Journal of Innovative Research in Technology},
        year = {},
        volume = {4},
        number = {7},
        pages = {622-629},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=145199},
        abstract = {Adders are the basic building blocks of many computational circuits. As a result, it is imperative to design fast adders and simultaneously optimize the power in these adders to the maximum extent possible. Carry Select Adder (CSA) is the most frequently used adder which works on the principle of pre computation of the sum and carry for each individual stage by assuming the carry in as ‘0’ and ‘1’. CSA employs additional Ripple Carry Adders (RCA) which induces an undesired increase in area as well as the delay as the carry is propagated through all stages. Thus the overall area and power consumption for CSA is also on the higher side. Hence, it is inevitable to opt for techniques to reduce the power consumption to achieve higher performance which is the eventual desired goal. This work involves Register Transfer Level design of 32-bit CSA with power and delay optimization techniques. The obtained results for the power consumed for each technique are hence analyzed and compared to obtain the best design which can be further implemented.},
        keywords = {Carry Adders, Register Transfer Level},
        month = {},
        }