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@article{161241,
        author = {K.Sunitha and S.Saranya },
        title = {Design of soc external attack detection and classification system},
        journal = {International Journal of Innovative Research in Technology},
        year = {},
        volume = {10},
        number = {2},
        pages = {1001-1007},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=161241},
        abstract = {In a real-world application context, hostile efforts on integrated circuit (IC) chips pose a threat to secure hardware systems. The vertical integration of systems, circuits, and packaging technologies is covered in this article along with overviews of physical assaults on cryptographic circuits, related weaknesses in an IC chip, and protection strategies. On-chip monitoring circuit design techniques to detect attacker attempts are described and put to the test using Si demonstrators. For safe IC chips, physical structures are investigated in order to create defences against multimodal side-channel attacks. In order to achieve avoidance, detection, and resilience against electromagnetic and laser attacks, the frontside complementary metal-oxide semiconductor (CMOS) circuits of a Si substrate are integrated with its backside buried metal (BBM) wirings},
        keywords = {Backside metal wirings, cryptography, electromagnetic (EM) attack, hardware security, laser fault injection attack, on-chip monitoring, power delivery network, side-channel attack, Si substrate attack},
        month = {},
        }