• ISSN: 2349-6002
  • UGC Approved Journal No 47859

CMOS Implementation of Low Complexity Multiplication Technique

  • Unique Paper ID: 142432
  • Volume: 2
  • Issue: 1
  • PageNo: 336-338
  • Abstract:
  • A low-complexity design for multiplication is primary requirement in Fast Fourier implementation. In this work an optimized multiplier for twiddle factor multiplier is designed. The proposed multiplier is slightly modified from the existing complex multipliers. A 3 bit multiplier is designed which results low power consumption with high speed. The presented complex multiplier with minimum complexity has with much less delay and simulation time, which reduces overall speed when implemented in FFT. The proposed CMOS implementation of multiplier is simulated in 45 nm scale using tanner tool version 14.11.
email to a friend

Cite This Article

  • ISSN: 2349-6002
  • Volume: 2
  • Issue: 1
  • PageNo: 336-338

CMOS Implementation of Low Complexity Multiplication Technique

Related Articles

Impact Factor
8.01 (Year 2024)
UGC Approved
Journal no 47859

Join Our IPN

IJIRT Partner Network

Submit your research paper and those of your network (friends, colleagues, or peers) through your IPN account, and receive 800 INR for each paper that gets published.

Join Now

Recent Conferences

NCSEM 2024

National Conference on Sustainable Engineering and Management - 2024 Last Date: 15th March 2024

Submit inquiry