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Low Power Level Converting Flip-Flop design by using Conditional Discharge Technique

  • Unique Paper ID: 142611
  • Volume: 2
  • Issue: 4
  • PageNo: 101-105
  • Abstract:
  • Clustered Voltage Scaling (CVS) is an effective way to reduce power consumption in digital integrated circuits. Level-converting flip-flops are the critical elements in the CVS scheme. A single edge implicit pulse-triggered level-converting flip-flop with a conditional clock technique is used in the existing system. It increases the data switching activity due to longer delay. So the power consumption is more. In proposed method LCFF with conditional discharge technique is used. By using this technique the extra switching activity is eliminated by controlling the discharge path when the input is stable high and the total power consumption is reduced and suitable for low power application. The proposed system is scaling in terms of power and delay. The simulations are done by using Mentor graphics tool in 130nm technology.
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Cite This Article

  • ISSN: 2349-6002
  • Volume: 2
  • Issue: 4
  • PageNo: 101-105

Low Power Level Converting Flip-Flop design by using Conditional Discharge Technique

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UGC Approved
Journal no 47859

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