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HIGH SPEED LOW POWER PERFORMANCE OF 8-BIT PARALLEL MULTIPLIER ACCUMULATOR USING MODIFIED RADIX-8 BOOTH ALGORITHM

  • Unique Paper ID: 144114
  • Volume: 3
  • Issue: 6
  • PageNo: 116-120
  • Abstract:
  • This paper proposes a new architecture of multiplier-and-accumulator (MAC) for high speed and low-power by adopting the new SPST implementing approach. This multiplier is designed by equipping the Spurious Power Suppression Technique (SPST) on a modified Booth encoder which is controlled by a detection unit using an AND gate. The SPST adder will avoid the unwanted addition and thus minimize the switching power dissipation In this we used Modelsim for logical verification, and further synthesizing it on Xilinx-ISE tool using target technology and performing placing & routing operation for system verification on targeted FPGA.
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Cite This Article

  • ISSN: 2349-6002
  • Volume: 3
  • Issue: 6
  • PageNo: 116-120

HIGH SPEED LOW POWER PERFORMANCE OF 8-BIT PARALLEL MULTIPLIER ACCUMULATOR USING MODIFIED RADIX-8 BOOTH ALGORITHM

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8.01 (Year 2024)
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