Performance Analysis for Synthesizing Voltage-Scaled Clock Distribution Networks

THEDLA SURYA BHARGAVI; SHUBHAKAR PARIKI

Performance Analysis for Synthesizing Voltage-Scaled Clock Distribution Networks

Authors: THEDLA SURYA BHARGAVI, SHUBHAKAR PARIKI

Unique Paper ID: 144656
Volume: 4
Issue: 1
PageNo: 298-303

Keywords: Synthesizing Voltage-Scaled Clock Distribution Networks

Abstract:
A low-voltage/swing clocking methodology is developed through both circuit and algorithmic innovations. The primary objective is to significantly reduce the power consumed by the clock network while maintaining the circuit performance the same. The methodology consists of two primary components: 1) a novel D-flip-flop (DFF) cell that maximizes power savings by enabling low-voltage/swing operation throughout the entire clock network and 2) a novel clock tree synthesis algorithm to ensure that the same timing constraints (i.e., clock frequency, skew, and slew) are satisfied. The proposed methodology is integrated within an industrial design flow. Experimental results on ISCASâ€™89 benchmark circuits demonstrate that the overall power consumed by the clock tree can be reduced by up to 27% and 44% in, respectively, 32- and 45-nm technologies while satisfying the same timing constraints. Furthermore, the proposed low-swing DFF cell maintains the clock-to-Q delay the same while achieving up to 32% and 15% power savings in the overall flip-flop power of the benchmark circuits at, respectively, 1- and 1.5-GHz clock frequencies.

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Cite This Article

ISSN: 2349-6002
Volume: 4
Issue: 1
PageNo: 298-303

Performance Analysis for Synthesizing Voltage-Scaled Clock Distribution Networks

Available:https://ijirt.org/Article?manuscript=144656

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UGC Approved
Journal no 47859

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