Optimized  Logic  Synthesis of reversible PLA

k.Vamshi Krishna; Vasavi Sikilambatla

Optimized Logic Synthesis of reversible PLA

Authors: k.Vamshi Krishna, Vasavi Sikilambatla

Unique Paper ID: 144658
Volume: 4
Issue: 1
PageNo: 308-311

Keywords: Reversible logic Quantum Computing PLA non-reversible counterparts.

Abstract:
Reversible logic have been motivated by consideration of zero-energy computation. Reconfigurability and structural regularity of Programmable Logic Devices caused wide use of it by the logic designers. In this paper, we propose a design algorithm for a PLA(Programmable Logic Array) with a newly designed low cost3 Ã— 3 reversible NMG (New Mux Gate) circuit for Implementing multi-output ESOP (Exclusive-OR Sum of Product) functions. In addition, we propose a heuristic to sort and to realize the product terms of ESOP functions in order to share the internal sub-products to reduce the number of gates in the proposed circuit. The proposed Algorithms make the design efficient with improvement in number of gates, garbage count and quantum cost metric than existing technique save ragely. Performance is also analyzed by using MCNC benchmark circuits.. The proposed architecture of this paper analysis the logic size and area using Xilinx 14.3.

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Cite This Article

ISSN: 2349-6002
Volume: 4
Issue: 1
PageNo: 308-311

Optimized Logic Synthesis of reversible PLA

Available:https://ijirt.org/Article?manuscript=144658

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UGC Approved
Journal no 47859

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