Efficient Pipelined CORDIC Architecture for Generation of Sine and Cosine Function

Ravi Mogili; Raju Katru; Kandukuri Shobha

Efficient Pipelined CORDIC Architecture for Generation of Sine and Cosine Function

Authors: Ravi Mogili, Raju Katru, Kandukuri Shobha

Unique Paper ID: 145250
Volume: 4
Issue: 8
PageNo: 447-452

Keywords: FPGA CORDIC Algorithm Folded & Unfolded Architecture serial and parallel pipelined CORDIC sine and cosine functions.

Abstract:
In processing the real world data Digital signal processing algorithms provide unbeatable efficiency. One of the DSP algorithms is COordinate Rotation DIgital computer (CORDIC). The beauty of CORDIC lies in the fact that by simple shift-add operations and theCORDIC has gained momentum for decades because of its less hardware complexity. CORDIC algorithm isvery simple and iterative process for performing various mathematical computations. Most of the literaturelacks in calculation of resources utilized by a particular CORDIC architecture. In this paper, serial, paralleland pipelined CORDIC architecture has been implemented for computing both sine & cosine functions.This paper makes an attempt to survey different forms of CORDIC algorithms and its architectures and applications explore implementation exact to FPGAs and the way the structure has been coded in VERILOG, synthesis evaluation are carried out making use of Xilinx ISim software and targeted on Xilinx FPGA synthesis device.

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Cite This Article

ISSN: 2349-6002
Volume: 4
Issue: 8
PageNo: 447-452

Efficient Pipelined CORDIC Architecture for Generation of Sine and Cosine Function

Available:https://ijirt.org/Article?manuscript=145250

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