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POWER OPTIMIZATION DESIGN TECHNIQUES FOR FPGA

  • Unique Paper ID: 146266
  • Volume: 4
  • Issue: 12
  • PageNo: 72-74
  • Abstract:
  • A variety of factors – from the micro to the macro, from conserving battery life to lessening global warming – has pushed power conservation rapidly up the list of system designers’ concerns. Engineers have ranked power consumption first in recent surveys on key design priorities or as a close second next to performance, density, and cost.FPGAs present unique challenges when it comes to power consumption. Armed with a good understanding of these challenges and new technology, techniques, and tools to meet them, system designers can realize the advantages of an FPGA-based portable system deployment. This is increasingly crucial as FPGAs are depended on more and more to provide flexibility and fast time to market in an expanding universe of applications.
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Cite This Article

  • ISSN: 2349-6002
  • Volume: 4
  • Issue: 12
  • PageNo: 72-74

POWER OPTIMIZATION DESIGN TECHNIQUES FOR FPGA

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