Multiprocessor Configuration of 8051 Microcontroller Chip

Vikalp Dwivedi; Prof Shripad G.Desai

Multiprocessor Configuration of 8051 Microcontroller Chip

Authors: Vikalp Dwivedi , Prof Shripad G.Desai

Unique Paper ID: 150767
Volume: 7
Issue: 9
PageNo: 281-287

Keywords: 8051 Microcontroller based system RS232 serial communication port systolic parallel processing parallel computers.

Abstract:
This paper extends the parallel operation of the 8051 microcontroller chip and presents the use of multiple 8051s that are connected to a common loop in a multiprocessor configuration. The 8051 multiprocessing implies many processors acting in some unified manner and connected so that data can be interchanged between them. There is generally a controlling or "talker" microcontroller that directs the activities of the remainder of the loop microcontrollers, or "listeners". One particular characteristic of a talker-listener loop is the frequent transmission of data between the talker and individual listeners. All data broadcast by the talker is received by all the listeners, although often the data is intended only for one or a few listeners. While some times, data is broadcast that is meant to be used by all the listeners. Communication through multiple 8051s use standard UART technology which assign unique addresses to all the listeners using mode 1, in this mode the listeners will waste a lot of processing time rejecting data not addressed to them. Mode 2 and 3 reduces processing time by enabling character reception based upon the state of SM2 in a listener and the state of bit ten in the transmitted character. A single strategy is used to enable a few listeners to receive data while the majority ignores the transmissions. This system is implemented and tested for transmitting data through talker as master and two listeners as slaves.

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Cite This Article

ISSN: 2349-6002
Volume: 7
Issue: 9
PageNo: 281-287

Multiprocessor Configuration of 8051 Microcontroller Chip

Available:https://ijirt.org/Article?manuscript=150767

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