Design and Implementation of PRPG with Low Transition Test CompressionTechnique

Hajari Manisha; Devendher kanoor; Gopi Kondra

Design and Implementation of PRPG with Low Transition Test CompressionTechnique

Authors: Hajari Manisha, Devendher kanoor, Gopi Kondra

Unique Paper ID: 144170
Volume: 3
Issue: 7
PageNo: 201-205

Keywords: Built-In Self-Test (BIST) Circuit Under Test (CUT) PRPG test data volume compression.

Abstract:
This project describes a low-power (LP) programmable generator capable of producing pseudorandom test patterns with desired toggling levels and enhanced fault coverage gradient compared with the best-to-date built-in self-test (BIST)- based pseudorandom test pattern generators. It comprised of finite state machine LFSR driving a phase shifterand it allows the device to produce binary sequence with preselected toggling activity. Generator is automatically controlled providingeasy and precise tuning. Furthermore, this paper introduces a test compression method to avoid repeated pattern generation for testingthe same device. The main highlight of this paper is to reduce the test data volume and test data memory.The proposed LPPRPG is designed using Verilog HDL.

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Cite This Article

ISSN: 2349-6002
Volume: 3
Issue: 7
PageNo: 201-205

Design and Implementation of PRPG with Low Transition Test CompressionTechnique

Available:https://ijirt.org/Article?manuscript=144170

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