An optimal approach of Priority Encoding based Reversible Comparators

D.Ashwini; D.Srikar; Gopi Kondra

An optimal approach of Priority Encoding based Reversible Comparators

Authors: D.Ashwini, D.Srikar, Gopi Kondra

Unique Paper ID: 144171
Volume: 3
Issue: 7
PageNo: 206-210

Keywords: Reversible logic comparators priority encoding quantum cost delay logic depth.

Abstract:
Lowering energy dissipation is the excellent goal in the world of VLSI circuit design. Traditional logic dissipates extrapower by dropping bits of information whereas reversibility recovers bit loss from the designated input-output mapping. Accordinglyreversible logic has turn out to be immensely trendy study subject and its applications have spread in various technologies. Comparators are a key aspect in most digital systems. In this paper we propose two new reversible comparator designs based on the suggestion of priority encoding. The designs consist of most of the time the Toffoli gates with each positive and negative control lines. The designs are optimized to reduce the quantum cost and delay. The proposed designs offer more growth in delay over the existing serial comparator and the equation based comparator. We also suggest modifications to the prevailing serial comparator and the equation based comparator for optimized performance.

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Cite This Article

ISSN: 2349-6002
Volume: 3
Issue: 7
PageNo: 206-210

An optimal approach of Priority Encoding based Reversible Comparators

Available:https://ijirt.org/Article?manuscript=144171

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