Implementationof High-Performance Double-Gate SOI Circuit Design

Bukya Balaji

Implementationof High-Performance Double-Gate SOI Circuit Design

Authors: Bukya Balaji

Unique Paper ID: 144472
Volume: 1
Issue: 7
PageNo: 680-683

Keywords: Circuit design CMOS double-gate SOI high-performance low-power.

Abstract:
Double-gate fully-depleted (DGFD) SOI circuits are viewed as the next generation VLSI circuits. This paper investigates the impact of scaling on the demand and challenges of DGFD SOI circuitdesign for low power and high performance.This paper presents the design of a45nm FD-DG SOI MOSFET and studies the impact of versionof channel doping and gate oxide thickness (TOX) on numeroustool parameters. Characteristics for the proposed MOSFEThave been obtained by way of considering most useful values of channeldoping and TOX. Cogendaâ€™s Visual TCAD device has been used forthe device simulation and parameter extraction.

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Cite This Article

ISSN: 2349-6002
Volume: 1
Issue: 7
PageNo: 680-683

Implementationof High-Performance Double-Gate SOI Circuit Design

Available:https://ijirt.org/Article?manuscript=144472

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