A Study of Globally Shared-Medium On-Chip Interconnect

Bukya Balaji

A Study of Globally Shared-Medium On-Chip Interconnect

Authors: Bukya Balaji

Unique Paper ID: 144473
Volume: 1
Issue: 5
PageNo: 1211-1214

Keywords: IC design RC/RLC Interconnection VLSI Systems.Transmission Line On-chip Interconnect.

Abstract:
Timing driven physical design, synthesis, and optimization tools necessity efficient closed-form delay models for assessing the delay associated with each net in an integrated circuit (IC) design.In this paper, we display that with straightforward optimizations, the traffic among different cores can be reservedrelatively low. This in turn permits simple shared-mediuminterconnects to be built using communication circuitsdriving transmission lines. This architecture compromises extremely low latencies and can support a large number ofcores without the need for packet switching, eradicatingcostly routers.

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Cite This Article

ISSN: 2349-6002
Volume: 1
Issue: 5
PageNo: 1211-1214

A Study of Globally Shared-Medium On-Chip Interconnect

Available:https://ijirt.org/Article?manuscript=144473

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