A Revision of On-Chip Interconnection Modeling for High Speed VLSI Systems

Bukya Balaji

A Revision of On-Chip Interconnection Modeling for High Speed VLSI Systems

Authors: Bukya Balaji

Unique Paper ID: 144532
Volume: 3
Issue: 1
PageNo: 392-396

Keywords: IC design RC/RLC Interconnection VLSI Systems

Abstract:
This paper presents closedâ€“form expressions for RC and RLC interconnection trees in current mode signaling, which can be employed in VLSI design tool. These investigative model expressions can be used for precise calculation of delay after the design clock tree has been located out and the design is fully routed.Assessment of these analytical models is several orders of magnitude faster than simulation using SPICE.

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Cite This Article

ISSN: 2349-6002
Volume: 3
Issue: 1
PageNo: 392-396

A Revision of On-Chip Interconnection Modeling for High Speed VLSI Systems

Available:https://ijirt.org/Article?manuscript=144532

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