Simulation of BIST based Multiplier using FPGA

G.Sathwik; Syed Mohammed Ali

Simulation of BIST based Multiplier using FPGA

Authors: G.Sathwik, Syed Mohammed Ali

Unique Paper ID: 145466
Volume: 4
Issue: 10
PageNo: 973-979

Keywords: No Keywords Found

Abstract:
The ever increasing applications of integrated circuits in the day-to-day useful electronic gadgets is the driving force for the development of low power designs of configurable hardware designs. High speed and low power are the main parameters that are targeted by modern circuit designers. Multipliers are the very important logic operational unit of any processing unit in digital signal processing applications. The speed and performance of multiplier is among the efficiency improvement parameters of any digital hardware design. Another important feature of hardware designs is self-testing ability. The built-in-self test (BIST) feature helps in quick diagnosis of the hardware functional authenticity. A low power Test Pattern Generator (TPG) is involved in the design for self-test design realization. The low power performance is analyzed with different operating clock frequency and Different FPGA devices with an improvement of around 10% of power with respect to previous design. The designs works at high speed of 3.288Gbps Throughput and 1.5 clock cycle Latency.

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Cite This Article

ISSN: 2349-6002
Volume: 4
Issue: 10
PageNo: 973-979

Simulation of BIST based Multiplier using FPGA

Available:https://ijirt.org/Article?manuscript=145466

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UGC Approved
Journal no 47859

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